VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS (10 Yrs)

VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS Folsom, CA 3 Months Role: Lead block-level physical design from RTL to GDSII. Must Have: 10 years exp, advanced nodes, and Fusion Compiler. Dexian stands at the forefront of Talent Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one of the largest technology and professional staffing companies and one of the largest minority-owned staffing companies in the United …